Codasip®, the leader in RISC-V Custom Compute, today announced the first commercial implementation of CHERI, a ground-breaking technology developed at the University of Cambridge. Capability Hardware Enhanced RISC Instructions (CHERI) technology was developed to improve system security and will now for the first time be available in a commercial offering, enabling secure-by-design products.
Memory safety is a primary concern for processor and SoC designers, device manufacturers, and end users. Cyberattacks pose an ever-growing threat and approximately 70% of OS and browser vulnerabilities documented in the Common Vulnerabilities and Exposures (CVE) program in the last two decades are attributed to software memory errors.
Codasip is adding built-in fine-grained memory protection to its recently launched 700 processor family by extending the RISC-V ISA with CHERI-based custom instructions and is also delivering the software environment to take advantage of CHERI technology, bringing a full software development flow to add memory protection.
Ron Black, chief executive officer, Codasip, said: “Unsafe and insecure products risk causing privacy violations, reputational damage and financial loss that are unacceptable, be it cars, routers, medical devices, or any other consumer product. Using Codasip’s CHERI technology, companies can take preventive security measures without having to wait for their vendors’ delivered patches.”
Professor Robert N. M. Watson, the University of Cambridge, said: “CHERI extends conventional hardware Instruction-Set Architectures (ISAs) with new architectural features to enable fine-grained memory protection and highly scalable software compartmentalization. The CHERI memory-protection features allow historically memory-unsafe programming languages such as C and C++ to be adapted to provide strong, compatible, and efficient protection against many currently widely exploited vulnerabilities.”
Codasip will be participating at the RISC-V Summit in Santa Clara, California, on November 7-8, showcasing their solutions and presenting a keynote and several technical topics.
Codasip announced today the first commercial implementation of CHERI, a ground-breaking technology developed at the University of Cambridge. Capability Hardware Enhanced RISC Instructions (CHERI) technology is designed to improve system security and will now be available in a commercial offering, enabling secure-by-design products.
Memory safety is paramount for processor and SoC designers, device manufacturers, and end users as cyberattacks pose an ever-growing threat. Approximately 70% of OS and browser vulnerabilities documented in the Common Vulnerabilities and Exposures (CVE) program in the last two decades are attributed to software memory errors.
Codasip is adding built-in fine-grained memory protection to its newly-launched 700 processor family by extending the RISC-V ISA with CHERI-based custom instructions and is also delivering the software environment to take advantage of CHERI technology, bringing a full software development flow to add memory protection.
Ron Black, CEO of Codasip, said: “Unsafe and insecure products risk causing privacy violations, reputational damage and financial loss that are unacceptable, be it cars, routers, medical devices, or any other consumer product. Using Codasip’s CHERI technology, companies can take preventive security measures without having to wait for their vendors’ delivered patches.”
Professor Robert N. M. Watson, from the University of Cambridge, added: “CHERI extends conventional hardware Instruction-Set Architectures (ISAs) with new architectural features to enable fine-grained memory protection and highly scalable software compartmentalization. The CHERI memory-protection features allow historically memory-unsafe programming languages such as C and C++ to be adapted to provide strong, compatible, and efficient protection against many currently widely exploited vulnerabilities.”
Codasip will be participating at the RISC-V Summit in Santa Clara, California, on November 7-8, showcasing their solutions and presenting a keynote and several technical topics.
Today, Codasip®, the leader in RISC-V Custom Compute, announced the first commercial implementation of CHERI, a ground-breaking technology developed at the University of Cambridge. Capability Hardware Enhanced RISC Instructions (CHERI) technology seeks to improve system security and will now be available in a commercial offering, enabling secure-by-design products.
As cyberattacks become more prevalent, memory safety is essential for processor and SoC designers, device manufacturers, and end users. Approximately 70% of OS and browser vulnerabilities documented in the Common Vulnerabilities and Exposures (CVE) program in the last two decades are attributed to software memory errors.
Codasip is adding built-in fine-grained
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