Codasip®, the leader in RISC-V Custom Compute, has announced its collaboration with Siemens EDA to offer the Tessent™ Enhanced Trace Encoder solution from the Tessent Embedded Analytics product line. Through this joint solution, developers will be able to efficiently trace and debug issues between silicon and software, and accurately understand real-time behaviors of even the most complex custom designs based on Codasip RISC-V processors™.
Codasip RISC-V processors are fully customizable and adaptable to the unique needs of an application. System designers can use the Codasip Studio™ toolchain to create optimal features and PPA (Power, Performance, Area). The combination of customizable processors and tools for processor design enables an automated approach to achieve Custom Compute. To make this customization usable for software developers, Codasip ensures that all tools—including the compiler and debugger—also support customization. This now includes the trace solution.
Including trace in an SoC significantly speeds up the time-consuming software development task and reduces the bring-up time and cost. Codasip chose to work with Siemens EDA for its Trace Encoder because the companies share a belief in product quality achieved efficiently throughout the product design flow. This focus on quality empowers innovation and delivers significant productivity gains for customers even in the most complex heterogeneous and custom designs.
The Tessent Enhanced Trace Encoder builds on the RISC-V standard produced by the Debug and Trace Working Group, which was led by representatives from Siemens who donated the Trace algorithm to the RISC-V International community. However, the solution from Siemens goes well beyond the RISC-V standard, offering a far more efficient tool with significant productivity gains in the development of the most complex systems, and it supports custom instructions. It conducts detailed examinations on systems to find the bug and its root cause. It is cycle-accurate, which means the developer gets insights into each and every instruction.
Mike Eftimakis, VP Strategy and Ecosystem at Codasip, said: “Codasip has high standards of quality when it comes to our processor IP. To ensure this results in outstanding systems, we wanted a trace solution that went much further than the RISC-V standard. The Tessent Enhanced Trace Encoder is optimized for exactly the types of complex and custom systems our customers are developing.”
Ankur Gupta, VP and GM of Siemens EDA’s Tessent division, added: “Tessent Embedded Analytics enables system-wide real-time debug and post-deployment analytics, helping SoC providers focus on the key task of producing high-quality, innovative products, and getting them to market quickly. Codasip has an outstanding reputation for assisting customers with just these kinds of requirements, and we’re delighted to be working together.”
Codasip will offer the Tessent Enhanced Trace Encoder solution directly to customers to streamline contractual complexity.
Today, Codasip and Siemens EDA announced a partnership to offer the Tessent™ Enhanced Trace Encoder solution from the Tessent Embedded Analytics product line for Codasip’s customizable RISC-V cores. The joint solution is designed to help developers trace and debug issues between silicon and software and accurately understand real-time behaviors of even the most complex custom designs.
Codasip RISC-V processors are fully customizable and adaptable to the unique needs of an application, allowing system designers to use the Codasip Studio™ toolchain to find the best software and hardware trade-offs and achieve optimal features and PPA (Power, Performance, Area). The combination of customizable processors and tools for processor design enables an automated approach to achieve Custom Compute.
Including trace in an SoC can significantly speed up the time-consuming software development task and reduce the bring-up time and cost. Codasip and Siemens EDA share a belief in product quality achieved efficiently throughout the product design flow and the Tessent Enhanced Trace Encoder builds on the RISC-V standard produced by the Debug and Trace Working Group. The solution goes beyond the RISC-V standard, offering a far more efficient tool with significant productivity gains in the development of the most complex systems. It supports custom instructions and conducts detailed examinations on systems to find the bug and its root cause.
Commenting on the partnership, Mike Eftimakis, VP Strategy and Ecosystem at Codasip, said: “Codasip has high standards of quality when it comes to our processor IP. To ensure this results in outstanding systems, we wanted a trace solution that went much further than the RISC-V standard. The Tessent Enhanced Trace Encoder is optimized for exactly the types
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